Decimation Lowpass Filters for SIGMA-DELTA Modulators - A Comparative Study

Inhaltsverzeichnis (Table of Contents)

• Introduction
• Overall Structure and Design Flow
• Oversampling Data Converters
• Hardware Realizations of Digital Filters
• Single-Stage Multirate FIR Filter
• Cascaded Structures

Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)

This thesis aims to compare various filter topologies used in the decimation of sigma-delta modulated digital signals, with a focus on efficient VLSI implementation. The goal is to present optimized filter architectures for a fifth-order 1-bit sigma-delta modulator with local feedback techniques used as the front-end A/D converter.

• Decimation of sigma-delta modulated digital signals
• Optimization of filter architectures for efficient VLSI implementation
• Comparison of different filter topologies
• Hardware realization of digital filters
• Influence of coefficient quantization on filter performance

Zusammenfassung der Kapitel (Chapter Summaries)

• Chapter 1: Provides a brief introduction to the principles of digital signal processing, focusing on FIR filters for acoustic applications.
• Chapter 2: Illustrates the proposed overall structure and the design flow of the decimation filter.
• Chapter 3: Presents the principles of oversampling data converters using sigma-delta techniques. The 5V fifth-order ΣA-modulator with 90dB dynamic range (SNR+THD) is presented, fabricated in 1.2μm CMOS technology.
• Chapter 4: Deals with typical hardware realizations of digital filters, including the "brute force" implementation of the multirate filter with identical filters running in parallel, as well as the LUT-based approach for small filter orders. The bit-serial approach and the bit-serial multiplier are investigated in detail due to their advantages for compact implementation.
• Chapter 5: Introduces the straightforward one-stage multirate FIR filter. A 4096 tap lowpass FIR filter is designed to meet the specifications. The influence of coefficient quantization is investigated, and the "block scaling" method for representing small values is presented. The single-stage implementation becomes less attractive as filter specifications increase.
• Chapter 6: Focuses on cascaded structures. The first stage is realized as a comb or sinc filter, decimating by a factor of 8 or 4. The conventional comb filter and a new architecture based on filter sharpening techniques are described. The unavoidable passband droop is compensated for by a subsequent lowpass FIR filter. Three examples, including comb-FIR cascade, sharpened comb-FIR cascade, and sharpened comb-half band filter cascade, are considered to compare filter realizations. The FIR filter realization using periodically time-varying coefficients (FIR-PTV filter) is also examined.

Schlüsselwörter (Keywords)

This study focuses on decimation lowpass filters for sigma-delta modulators, VLSI implementation, filter topologies, FIR filters, multirate architectures, coefficient quantization, comb filters, sinc filters, and FIR-PTV filters.