Decimation Lowpass Filters for SIGMA-DELTA Modulators - A Comparative Study

Table of Contents

1 Introduction

1.1 The z-Transform

1.2 Digital Filter Fundamentals

1.3 Decimation Filters

1.3.1 Multistage Decimation Filters

1.4 Comb Filters

1.4.1 Cascaded Comb Filters

1.4.2 Sharpened Comb Filter

1.5 Anti-Aliasing

1.5.1 Alias Rejection using Comb Filters

1.6 Finite Word-Length Effects

1.6.1 Number Representation

1.6.2 Roundoff Noise

1.6.3 Truncation and Rounding Errors

1.7 PTV(D)-Filter

1.7.1 Radix-r Signed Digit Number Representation

1.7.2 Quantization Error

1.7.3 Radix-3 SD Representation

1.7.4 Radix-4 SD Representation

1.7.5 The Design Flow for a PTV Filter

2 Design Environment

2.1 Σ∆-Converter Structure

2.2 Digital Filter Design Flow

2.3 Proposed Realization

3 Oversampling A/D Converters

3.1 Introduction

3.2 Fundamentals

3.2.1 Stability

3.2.2 Signal-to-Noise Ratio (SNR)

3.3 Nonideal Effects

3.4 DelSi - Simulation Tool

3.5 The IFLF5 Σ∆-Modulator

3.5.1 The Topology

3.5.2 Fully Differential SC Integrator

3.5.3 Input overload treatment

4 Hardware Realization

4.1 Introduction

4.2 LUT-Based Serial Distributed Multiplication

4.3 Multirate Decimation Filter

4.4 The Bit-Serial Approach for the FIR Filter Implementation in FPGAs

4.5 Modified FIR Filter in Direct Form

4.6 The Basic Building Blocks

5 Design of a One-Stage FIR Filter

5.1 Introduction

5.2 Coefficient Quantization

5.2.1 Technique to reduce Quantization Noise

5.3 Hardware Implementation

6 Designing a Multistage FIR Filter

6.1 Introduction

6.2 Proposed Structure for this Design

6.2.1 Specifications

6.2.2 Two-Stage Decimation

6.2.3 Three-Stage Decimation

6.3 The Comb - FIR Filter Cascade

6.3.1 Realization of the First Stage

6.3.1.1 Comb Filter 5th order

6.3.1.2 Comb Filter 6th order

6.3.1.3 Comb Filter 7th order

6.3.1.4 Comb Filter 8th order

6.4 The Comb - FIR Filter Cascade Design Example 1

6.4.1 Filter Properties

6.4.2 Hardware Requirements

6.4.3 An Modification of the Comb - FIR Filter Cascade

6.4.3.1 Filter Properties

6.4.3.2 Hardware Requirements

6.4.4 Sharpened Comb Filter

6.5 The Sharpened Comb Filter - FIR Compensator Cascade Design Example 2

6.5.1 Filter Properties

6.5.1.1 Quatizated Coefficients

6.5.2 Hardware Requirements

6.6 The Half-Band Filter

6.6.1 Determination of the Coefficients

6.7 The Comb - Half-Band Filter Cascade Design Example 3

6.7.1 The Half-Band Filter Section

6.7.2 The Front-End realized as Sharpened Comb Filter

6.8 The FIR Filter realized as a PTV Filter Structure

6.8.1 Description of the Topology

6.8.2 Hardware Requirements

6.9 Summary

7 Conclusions

Objectives & Topics

This thesis aims to compare various filter topologies for the decimation of sigma-delta modulated digital signals, specifically focusing on optimizing filter architectures for efficient VLSI implementation. The research explores the design of FIR filters, including multistage and cascaded structures like comb and sharpened comb filters, and evaluates their performance regarding stopband attenuation and hardware complexity.

• Comparative analysis of digital decimation filter topologies.
• Optimization of filter architectures for VLSI implementation.
• Investigation of comb, sharpened comb, and half-band filters in cascaded structures.
• Hardware realization techniques including bit-serial and PTV filter structures.
• Analysis of finite word-length effects and coefficient quantization in filter design.

Excerpt from the Book

Chapter Summary

1 Introduction: Provides fundamental theory on z-transforms, digital filter design, decimation processes, and specific architectures like comb and PTV filters.

2 Design Environment: Details the converter structure, filter design methodology, and proposed chip realization approach.

3 Oversampling A/D Converters: Discusses the principles of sigma-delta modulation, stability considerations, nonideal effects, and simulation tools.

4 Hardware Realization: Explores implementation techniques for FIR filters, focusing on LUT-based distributed arithmetic, bit-serial approaches, and multirate systems.

5 Design of a One-Stage FIR Filter: Presents the design, coefficient quantization, and implementation challenges for a single-stage high-order FIR decimator.

6 Designing a Multistage FIR Filter: Details cascaded filter designs, including comb-FIR, sharpened comb-FIR, and comb-half-band filter cascades for efficient decimation.

7 Conclusions: Summarizes the findings of the comparative study, highlighting the trade-offs between hardware complexity, filter order, and decimation performance.

Keywords

Sigma-Delta Modulators, Decimation Filters, FIR Filters, VLSI Implementation, Comb Filters, Oversampling, PTV Filters, Hardware Realization, Quantization Noise, Digital Signal Processing, Cascaded Filters, Sharpened Comb Filter, Half-Band Filters, FPGA, Circuit Design

Frequently Asked Questions

What is the primary objective of this thesis?

The thesis aims to compare various digital filter topologies for decimation in sigma-delta modulators to find optimized architectures suitable for efficient VLSI implementation.

What are the central thematic fields covered?

The work covers digital signal processing, filter theory (specifically FIR and comb filters), oversampling data conversion, and hardware realization strategies for integrated circuits.

What is the primary Forschungsfrage?

The research seeks to determine which cascaded filter architectures provide the best balance between meeting stringent stopband attenuation requirements and maintaining low hardware complexity.

Which scientific methods are employed?

The author uses mathematical modeling, MATLAB-based simulations for frequency response and coefficient quantization analysis, and empirical evaluation of hardware requirements in terms of logic blocks.

What topics are addressed in the main chapters?

The main chapters progress from fundamental theory (z-transforms, comb filters) to detailed design environments, hardware realization approaches, and comparative design examples of one-stage versus multistage (cascaded) filters.

Which keywords characterize this work?

Key terms include Sigma-Delta Modulators, Decimation Filters, FIR Filters, VLSI, Comb Filters, and PTV (Periodically Time-Varying) coefficients.

Why are cascaded structures preferred over one-stage filters in this study?

One-stage filters for these specific requirements result in prohibitively high filter orders and hardware costs, whereas multistage structures allow for "bulk" decimation using simpler comb filters.

What is the role of the 'sharpened' comb filter?

Sharpened comb filters are investigated because they offer improved alias rejection and reduced passband droop compared to conventional comb filters, albeit at the cost of higher hardware complexity.