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Table of Contents
Chapter I Evaluation of the filter expression in s-domain and z-domain
1.1) Laplace transform and Padè approximation
1.2) Impulse invariance technique
Chapter II Filter optimization – dynamic range analysis
2.1) State-Space realization
2.2) State-Space optimization
2.3) Hessenberg and Schur decompositions
2.4) Optimal capacitance distribution
Chapter III Comparison of discrete and continuous time approaches
3.1) State-Space realization in continuous time
Chapter IV Circuital realization of the filter
4.1) Synthesis of the state-space filter
4.2) Filter settings
4.3) First approach to the circuit
4.4) Impulse transient response of the circuit with ideal amplifiers
4.5) Step transient response of the circuit with ideal amplifiers
4.6) Sine transient response of the circuit with ideal amplifiers
4.7) Clock feedthrough
Chapter V Two-stage CMOS operational amplifier
5.1) Two-stage CMOS operational amplifier topology
5.2) Analysis of the amplifier
5.3) Frequency compensation
5.4) Integrator bandwidth
5.5) Considerations on the amplifier
5.6) Calculus of the transconductance by noise-optimisation
5.7) Calculus of the biasing current and design of the amplifier
Chapter VI Final schematic of the wavelet filter
6.1) Transmission gate and dummy gate
6.2) Impulse transient response
6.3) Step transient response
6.4) Sine transient response
6.5) Power consumption
6.6) Noise analysis
Chapter VII Considerations on the wavelet filter
Objective & Core Themes
The primary objective of this work is the design and implementation of a low-power, switched-capacitor CMOS wavelet filter specifically optimized for detecting QRS complexes in electrocardiogram (ECG) signals within pacemaker applications.
- Development of a wavelet filter utilizing state-space realization.
- Optimization of dynamic range, noise performance, and power consumption.
- Implementation of a two-stage CMOS operational amplifier for low-power operation.
- Verification through continuous and discrete-time simulation in a CMOS process.
- Mitigation of parasitic effects such as clock feedthrough using dummy switches.
Excerpt from the Book
1.1) Laplace transform and Padè approximation
A Gaussian function has generally the following parametric form: g(t) = a · e^(-(t-b)^2 / c^2). Let a = 1, b = 3 and c = 1. The previous expression can be rewritten as: g(t) = e^{-(t-3)^2}. To guarantee the causality of the filter in the evaluation of the Laplace transform, the Gaussian function has been delayed by choosing b = 3. In this way, as it is possible to see from Fig. 2, the Gaussian function lays on the right half of the plane.
Its first derivative is (Fig. 3): g'(t) = (-2t + 6) · e^{-(t-3)^2}. After applying the Laplace transform, it is necessary to apply the Padè approximation to arrive at a rational function which can lead us to the filter implementation [5].
The Padè approximation can be thought as a generalization of the Taylor polynomial. To be more precise, a Padè approximation of order (m, n) of a function f(x) at a point x0 is the rational function p(x)/q(x) where p(x) is a polynomial of degree m while q(x) is a polynomial of degree n and the formal power series of f(x)q(x)-p(x) in the point x0 begins with the term x^(m+n+1).
A first attempt to implement the filter has been carried out by using the Chebyshev polynomials because this allows approximating the Gaussian function in an interval and not only in a specific point. Unfortunately, the resulting filter, c(s), is instable as proven by the poles calculation (performed in Maple software).
Summary of Chapters
Chapter I: This chapter covers the mathematical foundation of the filter design, focusing on the Padè approximation of the Gaussian function and the application of the impulse invariance technique to transform the design into the z-domain.
Chapter II: This section details the state-space realization of the filter and provides the methodology for optimizing the dynamic range through controllability and observability gramians.
Chapter III: A comparison between discrete and continuous time approaches is presented, validating the preference for the discrete-time switched-capacitor realization for this specific application.
Chapter IV: The circuital synthesis of the filter is discussed, including the layout of the state-space block diagram and the design of parasitic-insensitive inverting and non-inverting integrators.
Chapter V: This chapter focuses on the design of the two-stage CMOS operational amplifier, covering topology, frequency compensation, noise optimization, and the calculation of biasing currents for low-power performance.
Chapter VI: The final schematic of the wavelet filter is presented, featuring improvements such as transmission gates and dummy gates to address clock feedthrough effects, along with simulation results.
Chapter VII: The work concludes by evaluating the overall performance and suggesting potential future enhancements for the wavelet filter design in pacemaker applications.
Keywords
Wavelet algorithm, ECG analysis, Pacemaker, CMOS filter, Switched-capacitor, State-space, Dynamic range, Operational amplifier, Low-power, Gaussian function, Padè approximation, Impulse invariance, Clock feedthrough, Noise optimization, Signal-to-noise ratio.
Frequently Asked Questions
What is the core purpose of this research?
The research focuses on designing a low-power analogue switched-capacitor CMOS wavelet filter suitable for integration into pacemakers to detect ECG signals, specifically the QRS complex.
What are the central thematic fields covered?
The work spans integrated circuit design, wavelet signal processing, low-power electronics, state-space control theory, and switched-capacitor filter design.
What is the primary research goal or question?
The goal is to implement a stable, high-performance, and low-power wavelet filter that can operate efficiently within the strict power constraints of a medical pacemaker device.
Which scientific methods are utilized in this work?
The methodology includes state-space realization for filter optimization, the impulse invariance technique for s-to-z domain transformation, and cadence simulations for testing transient responses and noise characteristics.
What topics are treated in the main body?
The main body covers the mathematical modeling of the Gaussian function, optimization of the filter matrices, circuit-level synthesis with CMOS integrators, amplifier design, and performance validation through transient analysis.
Which keywords characterize this work?
Key terms include wavelet algorithm, low-power design, switched-capacitor filter, CMOS operational amplifier, and ECG signal analysis.
Why is a discrete-time switched-capacitor approach preferred over a continuous-time one?
The switched-capacitor approach allows for larger signal voltage swings at the integrator output, provides a better dynamic range, and avoids the use of large resistor elements that are difficult to implement on-chip for low-power applications.
How is the clock feedthrough effect managed?
The design employs transmission gates and the insertion of dummy switches (or dummy gates) at the integrator inputs, which cancel the charge injection caused by the clock signal driving the transistors.
How does the author optimize for noise?
The author uses a state-space methodology to optimize the controllability and observability gramians, ensuring the dynamic range is maximized and noise is minimized relative to the signal strength.
What conclusion is drawn regarding the filter's power consumption?
The author concludes that while the current power consumption is acceptable for the demonstrated implementation, further scaling of capacitor values could significantly reduce power for final practical use in pacemakers.
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- Pietro Salvo (Autor:in), 2004, A Low-power Analogue SC-CMOS Filter suitable to implement the Wavelet Algorithm to analyse ECG signals in Pacemakers, München, Page::Imprint:: GRINVerlagOHG, https://www.diplomarbeiten24.de/document/198115
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