Cordic core with High throughput using 90nm SAED technology

Table of Contents

I. INTRODUCTION

II. OVERVIEW OF CORDIC CORE

2.1 Advantage

2.2 Disadvantage

2.3 Application

III. Working of cordic core

IV. RELATED WORK

4.1 Behavioral simulation

4.2 Simulation Of HDL design

4.3 Physical Design

4.4 Gate level simulation

V. CONCLUSION

Objectives and Topics

This work aims to implement a CORDIC (Coordinate Rotation Digital Computer) architecture using 90nm SAED technology to achieve a high-performance ASIC design characterized by reduced latency and power consumption. The research explores the efficient realization of elementary functions through shift-and-add operations instead of traditional multipliers.

• CORDIC algorithm fundamentals and operational modes.
• Hardware architecture design for VLSI implementation.
• Performance comparison between single and parallel module configurations.
• ASIC design flow, including RTL design, synthesis, and physical placement.
• Functional verification through behavioral and gate-level simulation.

Excerpt from the Book

Summary of Chapters

I. INTRODUCTION: Provides an overview of Digital Signal Processing and the need for efficient, hardware-optimized algorithms like CORDIC in VLSI design.

II. OVERVIEW OF CORDIC CORE: Details the operational principles, advantages, disadvantages, and various practical applications of the CORDIC algorithm.

III. Working of cordic core: Explains the iterative mathematical process of coordinate rotation and vectoring modes using shift-and-add operations.

IV. RELATED WORK: Describes the design methodology for single and parallel CORDIC modules, covering behavioral, HDL, physical, and gate-level simulation workflows.

V. CONCLUSION: Acknowledges the contributors and guidance provided during the development of the seminar work.

Keywords

CORDIC, VLSI, ASIC, Digital Signal Processing, Microprocessor, RTL Design, Functional Verification, Synthesis, Physical Design, Gate Level Simulation, Rotation Mode, Vectoring Mode, Throughput, Low Power, Hardware Efficiency

Frequently Asked Questions

What is the primary focus of this research paper?

The paper focuses on the ASIC implementation of a CORDIC (Coordinate Rotation Digital Computer) architecture using 90nm SAED technology, specifically aiming to reduce power consumption and latency.

What are the core thematic areas covered in this document?

Key areas include the theoretical basis of the CORDIC algorithm, architectural design for VLSI, comparison of module performance, and the comprehensive ASIC design flow.

What is the primary research objective?

The goal is to demonstrate an efficient hardware implementation of the CORDIC algorithm that avoids complex multipliers by utilizing shift-and-add arithmetic.

Which scientific method is utilized for the implementation?

The work employs a structured VLSI design flow consisting of HDL design, behavioral simulation, logic synthesis using the 90nm SAED library, physical design, and final gate-level simulation.

What topics are discussed in the main body?

The main body discusses the mathematical derivation of CORDIC iterations, the specific components required for hardware realization, and the step-by-step verification process for the design.

Which keywords best characterize this work?

Key terms include CORDIC, VLSI, ASIC, RTL Design, Functional Verification, Synthesis, Physical Design, and Gate Level Simulation.

Why is CORDIC considered "hardware-efficient"?

It is efficient because it replaces hardware-intensive multipliers with simple shift registers, adders, and small lookup tables to perform complex trigonometric and hyperbolic functions.

What is the difference between Rotation mode and Vectoring mode?

Rotation mode is used to rotate a vector by a specified angle, whereas Vectoring mode is typically used to calculate the magnitude and phase of a vector.

How does the parallel module design impact performance?

The dual-module parallel architecture is implemented specifically to increase throughput and reduce the overall processing time compared to a single-module design.

What role does the 90nm SAED technology play in this design?

The 90nm SAED library provides the standard cells and technical constraints necessary for the logic synthesis and physical placement of the CORDIC circuitry.