Cordic core with High throughput using 90nm SAED technology

Inhaltsverzeichnis (Table of Contents)

• I. INTRODUCTION
• II. OVERVIEW OF CORDIC CORE
  • 2.1 Advantage
  • 2.2 Disadvantage
  • 2.3 Application
• III. Working of cordic core
• IV. RELATED WORK
  • 4.1 Behavioral simulation
  • 4.2 Simulation Of HDL design
  • 4.3 Physical Design
  • 4.4 Gate level simulation
• V-CONCLUSION
• REFERENCES

Zielsetzung und Themenschwerpunkte (Objectives and Key Themes)

This work explores the implementation of a CORDIC (Coordinate Rotation Digital Computer) architecture using 90nm SAED technology with the goal of achieving reduced latency and power consumption. The CORDIC algorithm, known for its hardware efficiency, uses shift-and-add operations to compute elementary functions. The paper focuses on ASIC implementation and examines various design techniques to enhance the throughput and power efficiency of the CORDIC core.

• CORDIC Algorithm and its application in digital signal processing
• ASIC Implementation of CORDIC architecture
• Design optimization for reduced latency and power consumption
• High-throughput CORDIC core design
• Comparison of single and parallel CORDIC module performance

Zusammenfassung der Kapitel (Chapter Summaries)

• I. INTRODUCTION: This chapter provides an introduction to the field of digital signal processing and highlights the importance of special-purpose processors with customized architectures. It introduces the CORDIC algorithm as a simple and efficient solution for enhancing the speed and flexibility of signal processing tasks.
• II. OVERVIEW OF CORDIC CORE: This chapter delves into the fundamental concept of the CORDIC algorithm and its operation in both rotation and vectoring modes. It discusses the advantages of using CORDIC, including its hardware efficiency and ease of implementation in VLSI systems. It also explores the disadvantages of the CORDIC algorithm, such as the large number of iterations required for accurate results and its potential high power consumption.
• III. Working of cordic core: This chapter explains the CORDIC algorithm's working principle through an example, demonstrating the iterative rotation of a vector to achieve the desired angle. It introduces the concept of iterations and the use of an accumulator to determine the direction of rotation. The chapter further explains the two modes of CORDIC operation: rotation mode and vectoring mode.
• IV. RELATED WORK: This chapter discusses the implementation of the CORDIC algorithm at the architectural level. It describes the hardware components required for the CORDIC algorithm implementation, such as registers, shifters, adders/subtractors, and look-up tables. It also delves into the design of two different CORDIC modules: a single CORDIC module and a parallel CORDIC module. The chapter discusses the design flow for ASIC implementation, including behavioral simulation, HDL simulation, physical design, and gate-level simulation.

Schlüsselwörter (Keywords)

The primary focus of this text lies in the development and implementation of a CORDIC core for high-throughput digital signal processing applications. Key concepts explored include the CORDIC algorithm, its implementation in VLSI systems, ASIC design optimization techniques, reduced latency, power consumption, and high-throughput architectures. The work utilizes 90nm SAED technology for hardware realization and compares the performance of single and parallel CORDIC modules. This research utilizes various software tools for simulation and physical design, including Synopsys VCS, Design Compiler, and IC Compiler.